XC7Z020

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Zynq-7000 SoC mbụ nhazi ihe owuwu:
Ezinụlọ Zynq®-7000 dabere na nhazi ụlọ Xilinx SoC.Ngwaahịa ndị a na-ejikọta atụmatụ bara ụba nke dual-core ma ọ bụ otu-isi ARM® Cortex™-A9 (PS) na 28 nm Xilinx programmable logic (PL) n'ime otu ngwaọrụ.ARM Cortex-A9 CPUs bụ obi nke PS ma gụnyekwara ebe nchekwa on-chip, oghere ebe nchekwa mpụga, yana ọtụtụ oghere njikọ njikọta.Sistemụ Nhazi (PS) ARM Cortex-A9 Nkebi Ihe Nhazi Ngwa dabere (APU) • 2.5 DMIPS/MHz kwa CPU • Ugboro CPU: Ruo 1 GHz • nkwado multiprocessor ọnụnụ • ARMv7-A architecture • TrustZone® nchekwa • Thumb®-2 ntuziaka. set • Jazelle® RCT execution Environment Architecture • NEON™ media-processing engine • Single and double precision Vector Floating Point Unit (VFPU) • CoreSight™ na Program Trace Macrocell (PTM) • Ngụ oge na nkwụsịtụ • Ngụ oge nche atọ • Otu ngụ oge zuru ụwa ọnụ • Ihe nleba anya nke ngụ oge atọ ugboro abụọ • 32 KB Ọkwa 1 Ntuziaka nhazi ụzọ anọ na cache data (na-adabere na CPU nke ọ bụla) • 512 KB 8-way set-associative Level 2 cache (nkekeere n'etiti CPUs) • nkwado Byte-parity Ebe nchekwa On-Chip • On-chip boot ROM • 256 KB on-chip RAM (OCM) • nkwado Byte-parity Interfaces Mpụga ebe nchekwa • Multiprotocol dynamic memory controller • 16-bit ma ọ bụ 32-bit interfaces na DDR3, DDR3L, DDR2, ma ọ bụ Ncheta LPDDR2 • Nkwado ECC na ọnọdụ 16-bit • 1GB nke oghere adreesị site na iji abụ.le n'ọkwa nke 8-, 16-, ma ọ bụ 32-bit-obosara ebe nchekwa • Static ebe nchekwa interfaces • 8-bit SRAM data ụgbọ ala nwere ihe ruru 64 MB nkwado • Parallel NOR flash support • ONFI1.0 NAND flash support (1-bit ECC). ) • 1-bit SPI, 2-bit SPI, 4-bit SPI (quad-SPI), ma ọ bụ abụọ quad-SPI (8-bit) Oghere Usoro NOR flash 8-Channel DMA Controller • Ebe nchekwa-na-ebe nchekwa, ebe nchekwa-na. -peripheral, peripheral-to-memory, na ikposa-ịchịkọta azụmahịa nkwado I/O Peripherals na Interfaces • Abụọ 10/100/1000 tri-speed Ethernet MAC peripherals na IEEE Std 802.3 na IEEE Std 1588 ntụgharị 2.0 nkwado • Scatter-gather DMA support ikike • Nkwenye nke 1588 rev.2 PTP Frames • GMII, RGMII, na SGMII interfaces • Abụọ USB 2.0 OTG peripherals, nke ọ bụla na-akwado ruo 12 Endpoints • USB 2.0 comliant device IP core • Na-akwado na-aga, nnukwu ọsọ, zuru-ọsọ, na ala- ụdị ọsọ ọsọ • Intel EHCI USB nnabata • 8-bit ULPI mpụga PHY interface • Abụọ zuru CAN 2.0B kwekọrọ CAN interface ụgbọ ala • CAN 2.0-A na CAN 2.0-B na ISO 118981-1 ọkọlọtọ ndabara • Mpụga PHY interface • Abụọ SD / SDIO 2.0/MMC3.31 conliant controllers • Abụọ zuru-duplex SPI ọdụ ụgbọ mmiri na atọ mpụta mgbawa ahọrọ • Abụọ UARTs dị elu (ruo 1 Mb / s) • Nna ukwu abụọ na ohu I2C interfaces • GPIO nwere anọ 32-bit ụlọ akụ. , nke ihe ruru 54 bits nwere ike iji na PS I / O (otu ụlọ akụ nke 32b na otu ụlọ akụ nke 22b) na ruo 64 ibe n'ibe (ruo ụlọ akụ abụọ nke 32b) jikọọ na Programmable Logic • Ruo 54 mgbanwe. multiplexed I/O (MIO) maka ọrụ ntụtụ mpụta Interconnect • Njikọ bandwit dị elu n'ime PS na n'etiti PS na PL • ARM AMBA® AXI dabere • nkwado QoS na nkatọ.l nna ukwu maka latency na band.